Conventional integrated circuits contain a plurality of patterns of metal lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metal lines are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise eight or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A common method for forming metal lines or vias is known as “damascene”. Generally, this process involves forming an opening in the dielectric interlayer that separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a via. Excess metal material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
Copper has replaced aluminum because of its lower resistivity and higher reliability. However, copper still suffers from electro migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities increase.
In conventional interconnection structures, metal lines, which are typically formed of copper or copper alloys, are interconnected by vias. Etch stop layers (ESLs) are formed for better etch control. Diffusion barrier layers are typically formed to prevent copper from diffusing into neighboring low-k dielectric layers. The ESLs play an important role in the structure. Besides acting as etch stops, the ESLs also act as diffusion barrier layers preventing copper from diffusing into the respective overlying low-k dielectric layers, which are typically porous and vulnerable to copper “poisoning”.
The above-discussed structure, however, suffers performance problems when used in very small-scale integrated circuits. The ESLs are typically formed of a dielectric material having a higher k value than that of the low-k dielectric layers. As is well known in the art, the capacitance of a capacitor is proportional to the dielectric constant (k value) of the dielectric material between the capacitor plates. With ESLs having a higher k value, the effective k value of the material between the capacitor plates (metal lines) increases. Additionally, capacitance between closely located metal lines in the same metallization layer also increases. Consequently, RC delay of the integrated circuit increases.
A non-ESL method has been developed to solve this problem by forming metal cap layers instead of ESLs on the copper lines. The cap layers are typically formed of materials that suffer less from diffusion, and that can prevent copper from diffusing into the overlying low-k dielectric layers. Without the ESLs, the parasitic capacitance is reduced.
The non-ESL approach, however, has introduced another problem. A low-k dielectric layer typically has an inherent tensile stress. Stacked tensile layers tend to crack when the thickness is beyond a threshold called the cracking threshold. ESL layers typically have inherent compressive stress and can provide a structure support to the semiconductor structure, preventing overlying and underlying low-k dielectric layers from cracking. The lack of ESLs, therefore, may result in a weaker semiconductor structure.
In order to maintain the integrity of the semiconductor structures without sacrificing performance of the integrated circuits, a new method of forming interconnection structures is needed.